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| PDIUSBD12 USB interface device with parallel bus Rev. 06 -- 23 April 2001 Product data 1. Description The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments. This results in the fastest way to develop the most cost effective USB peripheral solution. The PDIUSBD12 fully conforms to the USB specification Rev. 1.1. It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPITM, OnNOWTM, and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. In addition, it also incorporates features like SoftConnectTM, GoodLinkTM, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. c c 2. Features s Complies with the Universal Serial Bus specification Rev. 1.1 s High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator s Compliant with most Device Class specifications s High-speed (2 Mbytes/s) parallel interface to any external microcontroller or microprocessor s Fully autonomous DMA operation Philips Semiconductors PDIUSBD12 USB interface device with parallel bus s Integrated 320 bytes of multi-configuration FIFO memory s Double buffering scheme for main endpoint increases throughput and eases real-time data transfer s Data transfer rates: 1 Mbytes/s achievable in Bulk mode, 1 Mbits/s achievable in Isochronous mode s Bus-powered capability with very good EMI performance s Controllable LazyClock output during suspend s Software controllable connection to the USB bus (SoftConnectTM) s Good USB connection indicator that blinks with traffic (GoodLinkTM) s Programmable clock frequency output s Complies with the ACPI, OnNOW and USB power management requirements s Internal Power-on reset and low-voltage reset circuit s Available in SO28 and TSSOP28 pin packages s Full industrial grade operation from -40 to +85 C s Higher than 8 kV in-circuit ESD protection lowers cost of extra components s Full-scan design with high fault coverage (>99%) ensures high quality s Operation with dual voltages: 3.3 0.3 V or extended 5 V supply range of 3.6 to 5.5 V s Multiple interrupt modes to facilitate both bulk and isochronous transfers. 3. Pinning information 3.1 Pinning Fig 1. Pin configuration. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 2 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 3.2 Pin description Table 1: Symbol DATA <0> DATA <1> DATA <2> DATA <3> GND DATA <4> DATA <5> DATA <6> DATA <7> ALE Pin description Pin 1 2 3 4 5 6 7 8 9 10 Type [1] IO2 IO2 IO2 IO2 P IO2 IO2 IO2 IO2 I Description Bit 0 of bidirectional data. Slew-rate controlled. Bit 1 of bidirectional data. Slew-rate controlled. Bit 2 of bidirectional data. Slew-rate controlled. Bit 3 of bidirectional data. Slew-rate controlled. Ground. Bit 4 of bidirectional data. Slew-rate controlled. Bit 5 of bidirectional data. Slew-rate controlled. Bit 6 of bidirectional data. Slew-rate controlled. Bit 7 of bidirectional data. Slew-rate controlled. Address Latch Enable. The falling edge is used to close the latch of the address information in a multiplexed address/ data bus. Permanently tied LOW for separate address/ data bus configuration. Chip Select (Active LOW). Device is in Suspend state. Programmable Output Clock (slew-rate controlled). Interrupt (Active LOW). Read Strobe (Active LOW). Write Strobe (Active LOW). DMA Request. DMA Acknowledge (Active LOW). End of DMA Transfer (Active LOW). Double up as VBUS sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. Reset (Active LOW and asynchronous). Built-in Power-on reset circuit present on chip, so pin can be tied HIGH to VCC. GoodLink LED indicator (Active LOW) Crystal Connection 1 (6 MHz). Crystal Connection 2 (6 MHz). If external clock signal, instead of crystal, is connected to XTAL1, then XTAL2 should be floated. Voltage supply (4.0 - 5.5 V). To operate the IC at 3.3 V, supply 3.3 V to both VCC and VOUT3.3 pins. USB D- data line. USB D+ data line. CS_N CLKOUT INT_N RD_N WR_N DMREQ EOT_N 11 13 14 15 16 17 19 I I,OD4 O2 OD4 I I O4 I I SUSPEND 12 DMACK_N 18 RESET_N GL_N XTAL1 XTAL2 20 21 22 23 I OD8 I O VCC 24 P D- D+ 25 26 A A 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 3 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Pin description...continued Pin 27 28 Type [1] P I Description 3.3 V regulated output. To operate the IC at 3.3 V, supply a 3.3 V to both VCC and VOUT3.3 pins. Address bit. A0 = 1 selects command instruction; A0 = 0 selects the data phase. This bit is a don't care in a multiplexed address and data bus configuration and should be tied HIGH. Table 1: Symbol VOUT3.3 A0 [1] O2 : Output with 2 mA drive OD4: Output Open Drain with 4 mA drive OD8: Output Open Drain with 8 mA drive IO2: Input and Output with 2 mA drive O4 : Output with 4 mA drive. 4. Ordering information Table 2: Packages 28-pin plastic SO 28-pin plastic TSSOP Ordering information Temperature range -40 C to +85 C -40 C to +85 C Outside North America PDIUSBD12 D PDIUSBD12 PW North America PDIUSBD12 D PDIUSBD12PW DH Pkg. Dwg. # SOT136-1 SOT361-1 5. Block diagram This is a conceptual block diagram and does not include each individual signal. Fig 2. Block diagram. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 4 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 6. Functional description 6.1 Analog transceiver The integrated transceiver interfaces directly to the USB cables through termination resistors. 6.2 Voltage regulator A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 k pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnect technology with an integrated 1.5 k pull-up resistor. 6.3 PLL A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL. 6.4 Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4x oversampling principle. It is able to track jitter and frequency drift specified by the USB specification. 6.5 Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. 6.6 SoftConnect The connection to the USB is accomplished by bringing D+ (for high-speed USB device) HIGH through a 1.5 k pull-up resistor. In the PDIUSBD12, the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through pin EOT_N. See Section 3.2 "Pin description" for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull-up voltage for the normally open-drain output of the DMA controller pin. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 5 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. 6.7 GoodLink Good USB connection indication is provided through GoodLink technology. During enumeration, the LED indicator will blink ON momentarily corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be permanently ON. Subsequent successful (with acknowledgement) transfer to and from the PDIUSBD12 will blink OFF the LED. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty equipment. This feature helps lower field support and hotline costs. 6.8 Memory Management Unit (MMU) and Integrated RAM The MMU and the integrated RAM buffer the difference in speed between USB, running in bursts of 12 Mbits/s and the parallel interface to the microcontroller. This allows the microcontroller to read and write USB packets at its own speed. 6.9 Parallel and DMA Interface A generic parallel interface is defined for ease-of-use, speed, and allows direct interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a memory device with 8-bit data bus and 1 address bit (occupying 2 locations). The PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The PDIUSBD12 also supports DMA (Direct Memory Access) transfer which allows the main endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both single-cycle and burst mode DMA transfers are supported. 6.10 Example of parallel interface to an 80C51 microcontroller In the example shown in Figure 3, the ALE pin is permanently tied LOW to signify a separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to any of the 80C51 I/O ports. This port controls the command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD12. The address phase will be ignored by the PDIUSBD12. The clock input signal of the 80C51 (pin XTAL1) can be provided by output CLKOUT of the PDIUSBD12. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 6 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus PDIUSBD12 80C51 INT_N A0 DATA [7:0] WR_N RD_N INTO/P3.2 ANY I/O PORT (e.g. P3.3) P [0.7:0.0]/AD [7:0] WR/P3.6 RD/P3.7 CLKOUT XTAL1 CS_N ALE SV00870 Fig 3. Example of a parallel interface to an 80C51 microcontroller. 7. DMA transfer Direct Memory Address (DMA) allows an efficient transfer of a block of data between the host and local shared memory. Using a DMA controller, data transfer between the PDIUSBD12's main endpoint (endpoint 2) and local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is set up for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation, the DMREQ pin will only be activated whenever the buffer is full, signalling that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput. When the host does not fill up the buffer completely (less than 64 bytes or 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 7 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 128 bytes for single direction ISO configuration), the DMREQ pin will be deactivated at the last byte of the buffer regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count. Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before the data is sent to the host. The only exception is at the end of DMA transfer, when the activation of pin EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfers, the local CPU and DMA controller have to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of pin DMACK_N automatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. 8. Endpoint description The PDIUSBD12 endpoints are sufficiently generic to be used by various device classes ranging from Imaging, Printer, Mass Storage and Communication device classes. The PDIUSBD12 endpoints can be configured for 4 operating modes depending on the Set mode command. The 4 modes are: Mode 0 Mode 1 Mode 2 Mode 3 Non-isochronous transfer (Non-ISO mode) Isochronous output only transfer (ISO-OUT mode) Isochronous input only transfer (ISO-IN mode) Isochronous input and output transfer (ISO-I/O mode). 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 8 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Endpoint Configuration Endpoint index 0 1 2 3 4 5 Transfer type Direction [1] Max. Packet size (bytes) 16 16 16 16 64 [4] 64 [4] 16 16 16 16 128 [4] 16 16 16 16 128 [4] 16 16 16 16 64 [4] 64 [4] Table 3: Endpoint number 0 1 2 Mode 0 (Non-ISO mode) Control Generic [2] Generic [2] [3] OUT IN OUT IN OUT IN Control Generic [2] Isochronous [3] Control Generic [2] Isochronous [3] Control Generic [2] Isochronous [3] OUT IN OUT IN OUT OUT IN OUT IN IN OUT IN OUT IN OUT IN Mode 1 (ISO-OUT mode) 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1 2 3 5 0 1 2 3 4 5 [1] [2] [3] [4] Mode 2 (ISO-IN mode) Mode 3 (ISO-I/O mode) IN: input for the USB host; OUT: output from the USB host. Generic endpoints can be used either as Bulk or Interrupt endpoint. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real-time applications and to increase throughput. This endpoint supports DMA access. Denotes double buffering. The size shown is for a single buffer. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 9 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 9. Main endpoint The main endpoint (endpoint number 2) is the primary endpoint for sinking or sourcing relatively large amounts of data. It implements the following features to ease this task: * Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput. Buffer switching is handled automatically. This results in transparent buffer operation. * DMA (Direct Memory Access) operation. This can be interleaved with normal I/O operation to other endpoints. * Automatic pointer handling during DMA operation. No local CPU intervention is necessary when `crossing' the buffer boundary. * Configurable endpoint for either isochronous transfer or non-isochronous (bulk and interrupt) transfer. 10. Command summary Table 4: Name Initialization commands Set Address/Enable Set Endpoint Enable Set mode Set DMA Data flow commands Read Interrupt Register Select Endpoint Device Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Read Last Transaction Status Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Read Buffer Write Buffer Selected Endpoint Selected Endpoint F4 00 01 02 03 04 05 40 41 42 43 44 45 F0 F0 Read 2 bytes Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read n bytes Write n bytes Device Device Device Device D0 D8 F3 FB Write 1 byte Write 1 byte Write 2 bytes Write/Read 1 byte Command summary Destination Code (Hex) Transaction 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 10 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Command summary...continued Destination Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Code (Hex) 40 41 42 43 44 45 F1 F2 FA F6 F5 Transaction Write 1 byte Write 1 byte Write 1 byte Write 1 byte Write 1 byte Write 1 byte None None None None Read 1 or 2 bytes Table 4: Name Set Endpoint Status Acknowledge Setup Clear Buffer Validate Buffer General commands Send Resume Read Current Frame Number Selected Endpoint Selected Endpoint Selected Endpoint 11. Command description 11.1 Command procedure There are three basic types of commands: Initialization, Data Flow and General commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. 11.2 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. 11.2.1 Set Address/Enable Code (Hex) -- D0 Transaction -- write 1 byte This command is used to set the USB assigned address and enable the function. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POWER ON VALUE ADDRESS ENABLE SV00825 ADDRESS: The value written becomes the address. ENABLE: A `1' enables this function. Fig 4. Set Address/Enable command: bit allocation. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 11 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 11.2.2 Set endpoint enable Code (Hex) -- D8 Transaction -- write 1 byte The generic/Isochronous endpoints can only be enabled when the function is enabled via the Set Address/Enable command. GENERIC/ISOCHRONOUS ENDPOINT: A value of `1' indicates the generic/isochronous endpoints are enabled. Fig 5. Set endpoint enable command: bit allocation. 11.2.3 Set mode Code (Hex) -- F3 Transaction -- write 2 bytes The Set mode command is followed by two data writes. The first byte contains the configuration bits. The second byte is the clock division factor byte. See Table 5 for bit allocation. Fig 6. Set mode command, Configuration byte. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 12 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Set mode command, Configuration byte: bit allocation Description These two bits set the endpoint configurations as follows: mode 0 (Non-ISO mode) mode 1 (ISO-OUT mode) mode 2 (ISO-IN mode) mode 3 (ISO-I/O mode) See Section 8 "Endpoint description" for more details. Table 5: 7 Bit Symbol ENDPOINT CONFIGURATION 4 SoftConnect A `1' indicates that the upstream pull-up resistor will be connected if VBUS is available. A `0' means that the upstream resistor will not be connected. The programmed value will not be changed by a bus reset. 3 INTERRUPT MODE A `1' indicates that all errors and "NAKing" are reported and will generate an interrupt. A `0' indicates that only OK is reported. The programmed value will not be changed by a bus reset. CLOCK RUNNING A `1' indicates that the internal clocks and PLL are always running even during Suspend state. A `0' indicates that the internal clock, crystal oscillator and PLL are stopped whenever not needed. To meet the strict Suspend current requirement, this bit needs to be set to `0'. The programmed value will not be changed by a bus reset. A `1' indicates that CLKOUT will not switch to LazyClock. A `0' indicates that the CLKOUT switches to LazyClock 1ms after the Suspend pin goes HIGH. LazyClock frequency is 30 kHz 40%. The programmed value will not be changed by a bus reset. 2 1 NO LAZYCLOCK 76 00 5 X 4 X 3 1 2 0 1 1 0 1 POWER ON VALUE CLOCK DIVISION FACTOR RESERVED SET_TO_ONE SOF-ONLY INTERRUPT MODE SV00862 See Table 6 for bit allocation. Fig 7. Set mode command, Clock division factor byte. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 13 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Clock division factor byte: bit allocation Description Table 6: Bit 7 Symbol SOF-ONLY Setting this bit to 1 will cause the interrupt line to be activated INTERRUPT MODE due to the Start Of Frame clock (SOF) only, regardless of the setting of Pin-Interrupt mode, bit 5 of set DMA. SET_TO_ONE This bit needs to be set to 1 prior to any DMA read or DMA write operation. This bit should always be set to 1 after power. It is zero after Power-on reset. The value indicates the clock division factor for CLKOUT. The output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up or down by the user. The minimum value of N is 0, giving a maximum frequency of 48 MHz. The maximum value of N is 11 giving a minimum frequency of 4 MHz. The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. 6 3 to 0 CLOCK DIVISION FACTOR 11.2.4 Set DMA Code (Hex) -- FB Transaction -- read/write 1 byte The set DMA command is followed by one data write/read to/from the DMA configuration register. DMA Configuration register: During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operations, the header will be skipped by the PDIUSBD12. See Section 11.3.4 "Read buffer" command. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. See Table 7 for bit allocation. Fig 8. Set DMA command. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 14 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Set DMA command: bit allocation Symbol ENDPOINT INDEX 5 INTERRUPT ENABLE Description A `1' allows for an interrupt to be generated whenever the endpoint buffer is validated (see Section 11.3.7 "Validate buffer" command). Normally turned off for DMA operation to reduce unnecessary CPU servicing. A `1' allows for an interrupt to be generated whenever the endpoint buffer contains a valid packet. Normally turned off for DMA operation to reduce unnecessary CPU servicing. A `0' signifies a normal interrupt pin mode where an interrupt is generated as a logical OR of all the bits in the interrupt registers. A `1' signifies that the interrupt will occur when Start of Frame clock (SOF) is seen on the upstream USB bus. The other normal interrupts are still active. When this bit is set to `1', the DMA operation will automatically restart. This bit determines the direction of data flow during a DMA transfer. A `1' means external shared memory to PDIUSBD12 (DMA Write); a `0' means PDIUSBD12 to the external shared memory (DMA Read). Writing a `1' to this bit will start DMA operation through the assertion of pin DMREQ. The main endpoint buffer needs to be full (for DMA Read) or empty (for DMA Write) before DMREQ will be asserted. In a single cycle DMA mode, the DMREQ is deactivated upon receiving DMACK_N. In burst mode DMA, the DMREQ is deactivated after the number of burst is exhausted. It is then asserted again for the next burst. This process continues until EOT_N is asserted together with DMACK_N and either RD_N or WR_N, which will reset this bit to `0' and terminate the DMA operation. The DMA operation can also be terminated by writing a `0' to this bit. Selects the burst length for DMA operation: 00 Single-cycle DMA 01 Burst (4-cycle) DMA 10 Burst (8-cycle) DMA 11 Burst (16-cycle) DMA Table 7: Bit 7 6 ENDPOINT INDEX 4 INTERRUPT ENABLE 5 INTERRUPT PIN MODE 4 3 AUTO RELOAD DMA DIRECTION 2 DMA ENABLE 1 to 0 DMA BURST 11.3 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 15 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 11.3.1 Read interrupt register Code (Hex) -- F4 Transaction -- read 2 bytes This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers. See Table 12 for bit allocation. Fig 9. Interrupt Register, byte 1. Table 8: 7 Read interrupt register, byte 1: bit allocation Description Bit Symbol SUSPEND CHANGE When the PDIUSBD12 did not receive 3 SOFs, it will go into suspend state and the Suspend Change bit will be HIGH. Any change to the suspend or awake state will set this bit HIGH and generate an interrupt. BUS RESET After a bus reset an interrupt will be generated this bit will be `1'. A bus reset is identical to a hardware reset through the RESET_N pin with the exception that a bus reset generates an interrupt notification and the device is enabled at default address 0. 6 DMA EOT: This bit signifies that DMA operation is completed. Fig 10. Interrupt Register, byte 2: bit allocation. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 16 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 11.3.2 Select Endpoint Code (Hex) -- 00 to 05 Transaction -- read 1 byte (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte. FULL/EMPTY: A `1' indicates the buffer is full, `0' indicates an empty buffer. STALL: A `1' indicates the selected endpoint is in the stall state. Fig 11. Select Endpoint command: bit allocation. 11.3.3 Read last transaction status register Code (Hex) -- 40 to 45 Transaction -- read 1 byte The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read. This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction. See Table 9 for bit allocation. Fig 12. Read last transaction status register. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 17 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Read last transaction status register: bit allocation Symbol PREVIOUS STATUS NOT READ DATA 0/1 PACKET SETUP PACKET ERROR CODE DATA RECEIVE/TRANSMIT SUSSESS Description A `1' indicates a second event occurred before the previous status was read A `1' indicates the last successful received or sent packet had a DATA1 PID A `1' indicates the last successful received packet had a SETUP token (this will always read `0' for IN buffers) See Table 10 "Error codes" A `1' indicates data has been received or transmitted successfully Table 9: Bit 7 6 5 4 to 1 0 Table 10: Error codes Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1111 Description No Error PID encoding Error; bits 7 to 4 are not the inversion of bits 3 to 0 PID unknown; encoding is valid, but PID does not exist Unexpected packet; packet is not of the type expected (= token, data or acknowledge), or SETUP token to a non-control endpoint Token CRC Error Data CRC Error Time Out Error Never happens Unexpected End-Of-Packet Sent or received NAK Sent Stall, a token was received, but the endpoint was stalled Overflow Error, the received packet was longer than the available buffer space Bitstuff Error Wrong DATA PID; the received DATA PID was not the expected one 11.3.4 Read buffer Code (Hex) -- F0 Transaction -- read multiple bytes (max. 130) The buffer pointer is not reset to the top of the buffer by the Read Buffer command. This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint). The data in the buffer are organized as follows: * byte 0: reserved; can have any value * byte 1: number/length of data bytes * byte 2: data byte 1 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 18 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus * byte 3: data byte 2 * etc. The first two bytes will be skipped in the DMA read operation. Thus, the first read will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. 11.3.5 Write buffer Code (Hex) -- F0 Transaction -- write multiple bytes (max. 130) The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be `0'. During DMA write operation, the first two bytes will be bypassed. Thus, the first write will write into Data byte 1, the second write will write into Data byte 2, etc. For non-isochronous transfer (bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host. Remark: There is no protection against writing or reading over a buffer's boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data in an OUT buffer are only meaningful after a successful transaction. The exception is during DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). 11.3.6 Clear buffer Code (Hex) -- F2 Transaction -- none When a packet is received completely, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the buffer is cleared, new packets will be accepted. 11.3.7 Validate buffer Code (Hex) -- FA Transaction -- none When the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 19 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 11.3.8 Set endpoint status Code (Hex) -- 40 to 45 Transaction -- write 1 byte A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it. When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID. Even when unstalled, writing Set Endpoint Status to `0' initializes the endpoint. STALLED: A `1' indicates the endpoint is stalled. Fig 13. Set endpoint status: bit allocation. 11.3.9 Acknowledge setup Code (Hex) -- F1 Transaction -- none The arrival of a SETUP packet flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for both IN and OUT endpoints. The microcontroller needs to re-enable these commands by the Acknowledge Setup command. This ensures that the last SETUP packet stays in the buffer and no packet can be sent back to the host until the microcontroller has acknowledged explicitly that it has seen the SETUP packet. The microcontroller must send the Acknowledge Setup command to both the IN and OUT endpoints. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 20 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 11.4 General commands 11.4.1 Send resume Code (Hex) -- F6 Transaction -- none Sends an upstream resume signal for 10 ms. This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write. 11.4.2 Read current frame number Code (Hex) -- F5 Transaction -- read 1 or 2 bytes This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant byte first. Fig 14. Read current frame number. 12. Interrupt modes Table 11: Interrupt modes SOF-ONLY INTERRUPT MODE [1] 0 0 1 [1] [2] [3] INTERRUPT PIN MODE [2] 0 1 X Interrupt types Normal [3] Normal + SOF [3] SOF only Bit 7 of Clock division factor byte of Set mode command (see Table 6). Bit 5 of Set DMA command (see Table 7). Normal interrupts from Interrupt Register. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 21 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 13. Limiting values Table 12: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI Ilatchup Vesd Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage latchup current electrostatic discharge voltage storage temperature total power dissipation Conditions Min -0.5 -0.5 Max +6.0 200 4000 [3] +150 95 Unit V mA V C mW VCC + 0.5 V VI < 0 or VI > VCC ILI < 15 A [1] [2] - - -60 - Equivalent to discharging a 100 pF capacitor via a 1.5 k resistor. Values are given for device only; in-circuit Vesd(max) = 8000 V. For open-drain pins Vesd(max) = 2000 V. Table 13: Recommended operating conditions Symbol VCC1 VCC2 VI VI/O VAI/O VO Tamb Parameter DC supply voltage (Main mode) DC supply voltage (Alternate mode) DC input voltage DC input voltage for I/O DC input voltage for analog I/O DC output voltage operating ambient temperature in free air Conditions apply to pin VCC only apply to pins VCC and Vout3.3 Min 3.6 3.0 0 0 0 0 -40 Max 5.5 3.6 5.5 5.5 3.6 VCC +85 Unit V V V V V V C 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 22 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 14. Static characteristics Table 14: DC characteristics (supply pins) Symbol ICC(susp) ICC Parameter suspend supply current operating supply current Conditions oscillator stopped and inputs connected to GND or VCC Min - - Typ - 15 Max 15 - Unit A mA Table 15: DC characteristics (digital pins) Symbol VIL VIH VHYS VOL VOH Parameter LOW level input voltage HIGH level input voltage hysteresis voltage LOW level output voltage HIGH level output voltage ST (Schmitt Trigger) pins IOL = rated drive IOL = 20 A IOH = rated drive IOH = 20 A Leakage current IOZ ILI OFF-state output current input leakage current OD (Open Drain) pins - - - - 5 5 A A 2.4 VCC - 0.1 - Conditions Min - 2.0 0.4 - Typ - - - - Max 0.8 - 0.7 0.4 0.1 - Unit V V V V V V V Input levels Output levels Table 16: DC characteristics (AI/O pins) Symbol ILZ VDI VCM VSE VOL VOH CIN ZDRV [1] ZPU [1] Parameter OFF-state leakage current differential input sensitivity differential common mode range single-ended receiver threshold static output LOW static output HIGH transceiver capacitance driver output resistance pull-up resistance Conditions 0 V < VIN < 3.3 V |(D+) - (D-)| includes VDI range Min - 0.2 0.8 0.8 Max 10 - 2.5 2.0 0.3 3.6 20 44 1.9 Unit A V V V V V pF k Leakage current Input levels Output levels RL of 1.5 k to 3.6 V RL of 15 k to GND pin to GND steady state drive SoftConnect = ON - 2.8 - 29 1.1 Capacitance Output resistance Pull-up resistance Includes external resistors of 18 1% on D+ and D-. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 23 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 15. Dynamic characteristics Table 17: AC characteristics (AI/O pins; FULL speed) [1] CL = 50 pF; RPU = 1.5 k on D+ to VCC; unless otherwise specified. Symbol Parameter Driver characteristics tR tF RFM VCRS tEOPT tDEOP tJR1 tJR2 tEOPR1 tEOPR2 rise time fall time differential rise/fall time matching (tR/tF) output signal crossover voltage source EOP width differential data to EOP transition skew receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions EOP width at receiver EOP width at receiver must reject as EOP; see Figure 15 must accept as EOP; see Figure 15 [2] [2] Conditions 10% to 90% of |VOH - VOL| 10% to 90% of |VOH - VOL| Min 4 4 90 1.3 Max 20 20 110 2.0 175 +5 Unit ns ns % V ns ns Driver timings see Figure 15 see Figure 15 160 -2 Receiver timings: -18.5 +18.5 ns -9 - 82 +9 40 - ns ns ns [1] [2] Test circuit, see Figure 21. Characterized but not implemented as production test. Guaranteed by design. tPERIOD CROSSOVER POINT EXTENDED CROSSOVER POINT DIFFERENTIAL DATA LINES SOURCE EOP WIDTH: tEOPT DIFFERENTIAL DATA TO SEO/EOP SKEW N * tPERIOD + tDEOP RECEIVER EOP WIDTH: tEOPR1, tEOPR2 SV00837 Fig 15. Differential data-to-EOP transition skew and EOP width. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 24 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Table 18: AC characteristics (parallel interface) Symbol tLH tAVLL tLLAX tCLWL tWHCH tAVWL tWHAX tWL tWDSU tWDH tWC tCLRL tRHCH tAVRL tRL tRLDD tRHDZ tRC [1] Parameter ALE HIGH pulse width address valid to ALE LOW time ALE LOW to Address transition time CS_N (DMACK_N) LOW to WR_N LOW time WR_N HIGH to CS_N (DMACK_N) HIGH time A0 Valid to WR_N LOW time WR_N HIGH to A0 transition time WR_N LOW pulse width write data setup time write data hold time write cycle time CS_N (DMACK_N) LOW to RD_N LOW time RD_N HIGH to CS_N (DMACK_N) HIGH time A0 Valid to RD_N LOW time RD_N LOW pulse width RD_N LOW to Data Driven time RD_N HIGH to Data high-Z time read cycle time Conditions Min 20 10 - 0 [1] 5 0 [1] 5 20 30 10 500 0 [1] 5 0 - - 500 [1] Max - - 10 - - - - - - - - - - - - 20 20 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ALE timings Write timings Read timings 20 Can be negative. Fig 16. ALE timing. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 25 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Fig 17. Parallel interface timing (I/O and DMA). Table 19: AC characteristics (DMA) Symbol Parameter Single-cycle DMA timings tWA tALRL tSHAH tAHRH tEL DMACK_N LOW pulse width DMACK_N LOW to DMREQ LOW time RD_N/WR_N HIGH to DMACK_N HIGH time DMACK_N HIGH to DMREQ HIGH time EOT_N LOW pulse width pins DMACK_N, RD_N/WR_N and EOT_N LOW all LOW 90 - 10 - - - 90 - 550 10 ns ns ns ns ns Conditions Min Max Unit Burst DMA timings tWSH tSHRL tELRL RD_N/WR_N HIGH time RD_N/WR_N HIGH to DMREQ LOW time EOT_N LOW to DMREQ LOW time 380 - - - 220 40 ns ns ns EOT timings 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 26 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus DMREQ tALRL tAHRH DMACK_N tWA tSHAH RD_N/WR_N tEL EOT_N (1) SV00874 EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW. Fig 18. Single-cycle DMA timing. Fig 19. Burst DMA timing. Fig 20. DMA terminated by EOT. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 27 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 16. Test information The dynamic characteristics of the analog I/O ports (D+ and D-) as listed in Table 17, were determined using the circuit shown in Figure 21. 1.5k IS INTERNAL TEST POINT 22 D. U. T. 15k CL = 50pF SV00849 Fig 21. Load for D+/D-. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 28 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 17. Package outline SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE vMA Z 28 15 Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.9 0.4 0.035 0.016 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 Fig 22. SO28 package outline. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 29 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 D E A X c y HE vMA Z 28 15 Q A2 pin 1 index A1 (A 3) A Lp L detail X 1 e bp 14 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 Fig 23. TSSOP28 package outline. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 30 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 31 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 18.5 Package related soldering information Table 20: Suitability of surface mount IC packages for wave and reflow soldering methods Package BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC [3], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO [1] Soldering method Wave not suitable not suitable [2] Reflow [1] suitable suitable suitable suitable suitable suitable not recommended [3] [4] not recommended [5] [2] [3] [4] [5] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 32 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 19. Revision history Table 21: Revision history Rev Date 06 20010423 CPCN Description Product specification; version 6. Supersedes PDUIUSBD12_5 of 19990108 (9397 750 04979). Data sheet modifications: * * * Converted to DBII template. Section 12 "Interrupt modes" added. Section 16 "Test information" created. 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 33 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus 20. Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 21. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 23. Trademarks ACPI -- is an open industry specification for PC power management, co-developed by Intel Corp., Microsoft Corp. and Toshiba GoodLink -- is a trademark of Royal Philips Electronics OnNow -- is a trademark of Microsoft Corp. SoftConnect -- is a trademark of Royal Philips Electronics. 9397 750 08117 (c) Philips Electronics N.V. 2001 All rights reserved. Product data Rev. 06 -- 23 April 2001 34 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Philips Semiconductors - a worldwide company Argentina: see South America Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Tel. +43 160 101, Fax. +43 160 101 1210 Belarus: Tel. +375 17 220 0733, Fax. +375 17 220 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Tel. +359 268 9211, Fax. +359 268 9102 Canada: Tel. +1 800 234 7381 China/Hong Kong: Tel. +852 2 319 7888, Fax. +852 2 319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Tel. +45 3 288 2636, Fax. +45 3 157 0044 Finland: Tel. +358 961 5800, Fax. +358 96 158 0920 France: Tel. +33 1 4728 6600, Fax. +33 1 4728 6638 Germany: Tel. +49 40 23 5360, Fax. +49 402 353 6300 Hungary: Tel. +36 1 382 1700, Fax. +36 1 382 1800 India: Tel. +91 22 493 8541, Fax. +91 22 493 8722 Indonesia: see Singapore Ireland: Tel. +353 17 64 0000, Fax. +353 17 64 0200 Israel: Tel. +972 36 45 0444, Fax. +972 36 49 1007 Italy: Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Tel. +81 33 740 5130, Fax. +81 3 3740 5057 Korea: Tel. +82 27 09 1412, Fax. +82 27 09 1415 Malaysia: Tel. +60 37 50 5214, Fax. +60 37 57 4880 Mexico: Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399 New Zealand: Tel. +64 98 49 4160, Fax. +64 98 49 7811 Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Tel. +63 28 16 6380, Fax. +63 28 17 3474 Poland: Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Tel. +34 33 01 6312, Fax. +34 33 01 4107 Sweden: Tel. +46 86 32 2000, Fax. +46 86 32 2745 Switzerland: Tel. +41 14 88 2686, Fax. +41 14 81 7730 Taiwan: Tel. +886 22 134 2451, Fax. +886 22 134 2874 Thailand: Tel. +66 23 61 7910, Fax. +66 23 98 3447 Turkey: Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 272 4825 Internet: http://www.semiconductors.philips.com (SCA72) 9397 750 08117 (c) Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 06 -- 23 April 2001 35 of 36 Philips Semiconductors PDIUSBD12 USB interface device with parallel bus Contents 1 2 3 3.1 3.2 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 8 9 10 11 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 11.4 11.4.1 11.4.2 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Analog transceiver . . . . . . . . . . . . . . . . . . . . . . 5 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . 5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 5 Philips Serial Interface Engine (PSIE) . . . . . . . 5 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Management Unit (MMU) and Integrated RAM. . . . . . . . . . . . . . . . . . . . . 6 Parallel and DMA Interface. . . . . . . . . . . . . . . . 6 Example of parallel interface to an 80C51 microcontroller . . . . . . . . . . . . . . . . . . . 6 DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Endpoint description . . . . . . . . . . . . . . . . . . . . . 8 Main endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . 10 Command summary . . . . . . . . . . . . . . . . . . . . 10 Command description . . . . . . . . . . . . . . . . . . . 11 Command procedure . . . . . . . . . . . . . . . . . . . 11 Initialization commands . . . . . . . . . . . . . . . . . 11 Set Address/Enable . . . . . . . . . . . . . . . . . . . . 11 Set endpoint enable . . . . . . . . . . . . . . . . . . . . 12 Set mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Set DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data flow commands . . . . . . . . . . . . . . . . . . . 15 Read interrupt register . . . . . . . . . . . . . . . . . . 16 Select Endpoint. . . . . . . . . . . . . . . . . . . . . . . . 17 Read last transaction status register . . . . . . . 17 Read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clear buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Validate buffer. . . . . . . . . . . . . . . . . . . . . . . . . 19 Set endpoint status . . . . . . . . . . . . . . . . . . . . . 20 Acknowledge setup. . . . . . . . . . . . . . . . . . . . . 20 General commands . . . . . . . . . . . . . . . . . . . . 21 Send resume . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read current frame number . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . . . . . . . Interrupt modes 21 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 Static characteristics. . . . . . . . . . . . . . . . . . . . 23 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 Dynamic characteristics . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Manual soldering. . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 28 29 31 31 31 31 32 32 33 34 34 34 34 (c) Philips Electronics N.V. 2001. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 23 April 2001 Document order number: 9397 750 08117 |
Price & Availability of PDIUSBD12PWDH
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